The EIP-96 is an Inline Cryptographic Accelerator designed to accelerate and offload the very CPU intensive IPsec, MACsec, SRTP, SSL, TLS and DTLS protocol operations. The In-line Multi-Protocol Engine is suited for communications processors and other general-purpose processors that require maximum data plane offload to dedicated security hardware. The Multi-Protocol Engine accommodates designs that already include Packet Classifiers (such as NPUs) as well as designs that require bulk crypto processing without any flow processing. In addition, the Multi-Protocol Engine can be used in various SoC architectures, even look-a-side architectures.