De-facto standard for graphics, high performance computing & networking

High Bandwidth Memory (HBM2 and HBM2E) Controller Cores and PHY IP Cores enable a cutting-edge, high-bandwidth, low latency and high density solution for all Graphics processing as well as high performance compute in a power efficient envelope.

HBM H-Series is designed to maximize performance in real-world applications. Architectural improvements enable a range of new configurations, including 3 standard Interfaces for easy integration and portability. New design supports up to 3.2Gbps per pin and can handle 2 psudo-channels in a single instance of the controller. Various clock ratios allows to reach high throughput without much routing constraints.

As SoC design complexity has increased over the years. Power, performance, area and latencies have become more important for the design to stay relevant. SoC designers at this juncture needs more support than ever. We created "Support & Design Acceleration Kit" keeping this in mind. So they can get IP integration tools, reference designs, design guidelines throughout the design cycle.