The Alma Technologies SHA1 IP core is a high performance implementation of the SHA-1 Message Digest algorithm, a one-way hash function, compliant with FIPS 180-1.

The core is composed of two main units, the SHA1 Engine and the Padding Unit as shown in the block diagram. The SHA1 Engine applies the SHA1 loops on a single 512-bit message block, while the Padding Unit splits the input message into 512-bit blocks and performs the message padding on the last block of the message.

The processing of one 512-bit block is performed in 82 clock cycles and the bit-rate achieved is 6.24Mbps / MHz on the input of the SHA1 core.