Chevin Technology's 10G & 25G UDP Ethernet IP is FPGA Synthesisable EndPoint with Checksum Offload for ultra low-latency connectivity.

The 10G & 25G UDP IP cores simplify FPGA integration of an ultra fast UDP/IP layer in any FPGA by handling the complete Ethernet frame assembly.

A simple AXI4 streaming interface is all that is required to start sending and receiving UDP datagrams, and only the "user data" payload is exchanged between the application and the UDP block. For a single port application the port number can be set to a constant, hard coded or software configurable. A multi- port application is supported by a single UDP IP core by using the udp_port sideband embedded in the streaming interface.