The Western Digital SweRV Core™ EL2 is a single issue, RV32IMC, single-issue core with a 4-stage in-order pipeline. Like the EH1 and EH2, it supports optional instruction and data closely coupled memo...

The SweRV EH1 Support package (SSP) contains everything needed to deploy a Western Digital SweRV EH1 core in an integrated circuit

The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing th...

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

Cortus have applied their many years of processor design expertise to the RISC-V ISA. Concentrating on the needs of the embedded designer and leveraging the success of their APS family of processors. ...

The icyflex-V 32-bit processor core is based on the RV32IMC open-instruction set architecture (ISA) defined by the RISC-V foundation and, as such, is supported by standard state-of-the-art development tools (both open-source and proprietary).

SkyeChip

The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core.

IQonIC Works RV32EC_P2 Core is a 2-stage pipeline RISC-V processor core, designed to meet the needs of small, low-power embedded applications, running only trusted firmware.

IQonIC Works RV32IC_P5 Core is a larger, 5-stage pipeline core RISC-V processor, designed to meet the needs of medium-scale embedded applications that require higher performance, cache memories, and running a mix of trusted firmware and user application code.

The 32-bit N45 is an 8-stage superscalar processor that supports RISC-V specification, including (IMAFD) standard instructions, 16-bit compression instructions, and for user-level interrupts. It iss...

The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructi...

The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP instructi...

The 32-bit RISC CPU core features a 32x16 bit MAC capable of single cycle MAC operations, which enhances execution times of DSP instructions that are critical to DSP applications. The 32 bit datapath has been designed to minimize data, branch and structural hazard-related stalls. It can operate in five operating modes and has a shadow register bank, that provides fast context switching for high priority interrupts.

32-bit RISC-V core with in-order pipeline.Tiny Linux-capable processor for IoT applications.

AndesCore™ N25 is a 32-bit CPU IP core based on AndeStar™ V5m Instruction Set Architecture, which support RISC-V RV32IMAC extensions from the latest developments in computer architecture a...

Compact High-Speed 32-bit CPU Core with DSP

The eSi-3200 32-bit CPU is the mid-range member in the eSi-RISC family of processor cores.

AndesCore™ D23 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5/V5e architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly use...

EMSA5-FS is a 32-bit, in-order, single-issue, five-stage pipeline processor supporting the open standard RISC-V instruction set architecture (ISA).

R core can work standalone or integrate with several RiVAI-V cores in heterogeneous multicore products. Heterogeneous multicore architecture unleashes energy efficiency of each individual core and com...

>The eSi-3250 32-bit CPU is targeted specifically for applications with high performance requiring caching, due to the use of slow on-chip memories such as eFlash, off-chip memories, or core/bus ratios greater than 1.

• RISC-V 32bit General Purpose Tiny Core
• ISO26262:2018 ASIL D compliant SEooC IP
• RISC-V Solution by Collaborating with Partners

RISC-V 32bit General Purpose Tiny Co...

Off-loading heavy calculations from microcontrollers The DR1000C is a parallel processor IP that is ideal for offloading high-load arithmetic processing (model predictive control, AI inference...

AndesCore™ N22 is a 32-bit 2-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications that require low energy consumption and small area.

With domain specific architecture, we optimize customer silicon PPA with agile development of RISC-V custom instruction set.

The CCRV32ST-S is a synthesisable Verilog model of a high performance 32-bit RV32GC System-on-Chip.

The CC100-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The ...

The CC150-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor. The model is highly configurable, and particularly suitable for system-on-a-chip (SoC) designs. The ...

The CC100-S is a synthesisable Verilog model of a high performance 32-bit RISC processor based System-on-Chip. The model is highly configurable and embeds a wide range of peripherals. The SoC can be e...

The CC150-S is a synthesisable Verilog model of a high performance 32-bit RISC processor based System-on-Chip. The model is highly configurable and embeds a wide range of peripherals. The SoC can be e...

The E2 Series is highly optimized for area and power while still offering class-leading performance. Targeted for microcontroller and embedded devices, the E2 Core can be configured to be as small as ...

The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently ...

The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected To...

The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA's F standard extension. Th...

The E3 Series is highly-integrated and feature-rich. It includes the E31 Core, which is the most widely deployed RISC-V core in the world. E3 embedded cores have a 5-6 stage pipeline, offering a great...

The SiFive E31 Standard Core is the world's most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core ...