Frame Buffer Compression IP Subsystem for TCON IC Manufacturers Launched by Hardent

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Proven IP subsystem enables TCON IC manufacturers to leverage new Embedded DisplayPort low power features and significantly reduce frame buffer area using VESA DSC.

January 27, 2022 -- Hardent, Inc., a leading provider of video compression IP cores, today announced the availability of a new VESA® Display Stream Compression (DSC) Frame Buffer Compression IP Subsystem. Designed for Timing Controller (TCON) Integrated Circuits (ICs) with Embedded DisplayPort (eDP) interfaces, the IP subsystem will enable a significant reduction in frame buffer area when using the new eDP 1.5 low power mode.

eDP 1.5 leverages a new Panel Replay protocol for enhanced panel self-refresh capability. During self-refresh, the GPU and eDP 1.5 interface enter a low power state to conserve system power and extend battery life. The last frame transferred is stored in the Display Panel Frame Buffer located in the Panel TCON IC and is replayed in a loop while the GPU and the eDP link go into a low power state.

The Display Panel Frame Buffer can be compressed using VESA DSC. If the GPU supports DSC, the frames are already compressed when they are transferred to the Panel TCON IC. However, if the GPU source doesn’t support DSC, the Panel TCON IC may also integrate a DSC compression engine so that the stored frames are always compressed, therefore reducing the required area to implement the Panel Display Frame Buffer. To save further power, partial updates of the Display Panel Frame Buffer are supported. Only image regions that have changes are then transferred from the GPU to the Display Panel over the eDP link.

“Designing an efficient frame buffer compression subsystem that supports all the enhanced eDP low power features and includes local DSC compression capabilities can be a challenge for designers unfamiliar with the specifics of the VESA DSC and eDP standards,” explains Simon Bussières, Product Manager at Hardent. “Our complete subsystem significantly lowers the implementation risk of integrating DSC into the Display Panel TCON IC and can be fully tailored to meet the pixel throughput requirements of many target applications including laptops and automotive displays.”

“Much of the success of the VESA eDP standard can be attributed to open collaboration between the video source and sink chip companies that enable the eDP ecosystem, including companies like Hardent, which provides IP to the chip industry,” said Craig Wiley, senior director of marketing at Parade Technologies, VESA board member and editor of the eDP standard. “Hardent played a key role in defining the frame buffer Display Stream Compression protocols for the eDP 1.5 spec, which will result in improved image quality and power savings. Hardent is also making important contributions for the eDP automotive extensions now in definition.”

Key Features of the Hardent DSC Frame Buffer Compression IP Subsystem

• Frame buffer area reduction by 66% and more
• Visually lossless quality for all types of images and videos
• Includes silicon proven, small footprint, low power DSC v1.2a Encoder and DSC v1.2a Decoder IPs
• Supports display resolutions of 8K (FUHD) at 60 frames per second (fps) and above
• Partial frame buffer updates (Selective Region Updates) supported
• Single frame buffering with very low latency

The Hardent VESA DSC Frame Buffer Compression IP subsystem is available immediately. For more information, visit Hardent’s VESA DSC IP product web page.

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