Leti details move to 10nm, 7nm FD-SOI process in Europe

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French research centre CEA-Leti is setting up a cleanroom to develop modules for a 10nm low power process technology using fully depleted silicon on insulator (FD-SOI) that will move to 7nm in the future.

www.eenewseurope.com/, Jun. 28, 2023 – 

The process, discussed at the Leti Innovation Days this week, will use planar transistors to be compatible with existing designs at 18, 22 and 28nm and will also include embedded non volatile memory (eNVM). This is funded by the French government separately from the EU Chips Act.

Europe teams on next generation FD-SOI technology

ST, GlobalFoundries to build 300mm FD-SOI fab at Crolles

The 3000sq m clean room in Grenobles will break ground in September to develop the modules for ST Microelectronics and GlobalFoundries who currently make FD-SOI devices. The new process will be ready in three years, aligned with the new ST/GF joint venture fab in neighbouring Crolles, and use wafer from Soitec. The modules will also include adaptive back bias developed by Dolphin Design in Grenoble to further reduce the power consumption.

Researchers are looking at FRAM for the embedded memory, where the memory cells sit in the metal layers and are a back end process. This will be a shrink of existing memory cells. GF already provides MRAM eNVM for its 22FDx process.

Leti plans to set up a pilot line that will take the FDSOI process down to 7nm, the limit for immersion lithography.

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