Cadence RTL design tool claims 5x faster RTL convergence

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Cadence said users of its new Joules RTL Design Studio can achieve physical estimates quickly and accurately, claiming up to 5X productivity and up to 25% QoR improvements in the RTL.

www.embedded.com/, Jul. 24, 2023 – 

Cadence Design Systems has introduced an RTL (register transfer level) debugging assistant system to help RTL designers be more productive, giving them fast, accurate insights into what could be wrong and why, and provide actionable guidance on improving the RTL.

Its new Joules RTL Design Studio provides front-end designers with access to digital design analysis and debugging capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff. Cadence said users can achieve physical estimates quickly and accurately, claiming up to 5X productivity and up to 25% quality of results (QoR) improvements in the RTL.

The new tool expands upon Cadence's existing Joules RTL Power Solution, addressing all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC). The new Joules RTL Design Studio is effectively an intelligent RTL debugging assistant system, providing early PPAC metrics as well as actionable debugging information throughout the design cycle–logical, physical, and production implementation–so engineers can explore "what-if" scenarios and potential resolutions to minimize iterations and improve design outcomes.

It is part of a unified cockpit and integrates with other Cadence tools, including the generative AI solution Cadence Cerebrus Intelligent Chip Explorer, which means users can access all analysis and design exploration features from a single GUI for optimal QoR. Hence RTL designers are able to get physical design feedback, localization and categorization of violations, bottleneck analysis and cross-probing between RTL, schematic, and layout.

Chin-Chi Teng, senior vice president and general manager of the digital & signoff group at Cadence, said, "Now RTL designers can rapidly access all the physical information needed for PPAC debug without having to wait for implementation, which previously took days or weeks. Joules RTL Design Studio gives designers visibility into the challenges when they can still be addressed easily, ultimately speeding time to market."

In the announcement from Cadence, there were a number of customer endorsements, including Alibaba, Arm, Mediatek and Socionext.

For Alibaba's T-Head division, Zejian CAI, responsible for COT methodology, said, "Due to power density increases in today's SoCs, design energy efficiency has become even more important. To improve energy efficiency, we made considerable efforts to enhance RTL-level optimization. Now, by leveraging Joules RTL Design Studio from Cadence, we can achieve efficient and accurate power breakdown analysis much earlier in the design phase. The tool's power prediction capability allows quick RTL optimization iterations so our design team can speed RTL optimization effectively."

Mark Galbraith, vice president of productivity engineering, Arm, added that identifying RTL bottlenecks early in the design cycle was critical in IP development and enables quicker updates, higher quality RTL and improved PPA. He said for Arm specifically, the new RTL tool from Cadence helped identify problem points associated with congestion and deep logic, saving significant time in finding the root cause.

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