Siemens launches Tessent tool for Verilog and RTL design for test

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Siemens Digital Industries Software has launched a tool to boost design-for-test (DFT) for complex chip developments at both the Verilog and RTL levels.

www.eenewseurope.com/, Oct. 10, 2023 – 

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern generation) to identify and address outlier blocks and take appropriate measures.

This automates the analysis and insertion of test points, wrapper cells, and x-bounding logic earlier in the design flow, which can help customers shorten design cycles and improve the testability of their designs. A key ability of the tool is to handle complex Verilog and SystemVerilog constructs while maintaining the look and feel of the original RTL design.

The RTL Pro tool works with the Siemens Tessent DFT tools for analysis of RTL complexity and its adaptability for test point insertion, evaluating whether the customer's RTL structure can be edited efficiently, which is a critical factor when adding test points throughout the design. This innovative functionality can help customers reduce their design turn-around-time and improve time-to-market.

Siemens also supports the ability of third-party tools to optimize area and timing when adding DFT logic prior to synthesis, leaving only scan insertion for the gate level. Design insertion happens at the RTL development stage, with RTL output, allowing seamless integration with third-party synthesis and verification software. In addition, RTL Pro generates design files that work with any downstream synthesis or verification flows, without requiring a closed-flow process.

Siemens automates 2.5D and 3D IC design-for-test

"Adopting Tessent RTL Pro for our next-generation automotive semiconductor design allows us to extend our shift-left strategy and reduce the iterations of the conventional design flow. This is all possible while maintaining our best-in-class coverage and pattern count," said Tatsuya Saito, senior principal EDA engineer, Digital Design Technology Department, Shared R&D EDA Division at Renesas Electronics which is using the tool.

"The ability to provide our back-end and verification teams with the same, complete design view containing all Tessent IP, including VersaPoint test points in RTL, is paramount for our competitiveness," he said.

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