AndesCore™ N25 is a 32-bit CPU IP core based on AndeStar™ V5m Instruction Set Architecture, which support RISC-V RV32IMAC extensions from the latest developments in computer architecture and boosted by Andes Technology s own performance enhancement instructions. Designed with a fast and efficient 5-stage pipeline, N25 reserved one full cycle time for embedded SRAM such as Caches and Local Memories to match with the CPU core which operates fast as over 1 GHz with 28nm process technology. Performance options includes such as high speed or small gate count multiplier, and choice of Dynamic Branch Prediction with Branch Target Buffer, Branch History Table and Return Address Stack. Design features includes AXI or AHB bus master port with clock frequency flexibly configurable as fraction of CPU clock, AHB slave port for direct bus master accesses to Local Memories, Vectored interrupt dispatch for the integrated Platform-Level Interrupt Controller (PLIC), and Exception Redirection that automatically triggers debugging events.

AndeStar V5m 32-bit Instruction Set Architecture

RISC-V compliant plus Andes performance enhancement extensions

Branch Prediction with large history buffers to accelerate complex programs

Individually configurable Caches and Local Memories for Instruction and Data

Native support of AXI/AHB bus master and AHB bus slave ports

Fast and compact design to reach over 1 GHz at 28nm

Product packages of N25 with CPU Subsystem, and N25 with AHB Platform