The GRCAN core is a CAN controller with an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller.

GRCANFD is a VHDL IP core implementing a CAN-FD controller compatible with both CAN 2.0B and CAN-FD. It consists of an internal CAN-FD codec and a top layer handling the configuration and control of the IP.

The CAN_OC core is a Philips SJA1000 compatible CAN core with a AHB slave backend.

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for si...

The GR716 features a fault-tolerant LEON3 SPARC V8 processor, communication interfaces and on-chip ADC, DAC, Power-on-Reset, Oscillator, Brown-out detection, LVDS transceivers, regulators to support f...

The GR765 is the next-generation radiation-hardened fault-tolerant octa-core system-on-chip, with the bootstrap option to select between LEON5FT SPARC V8 and NOEL-V RV64 RISC-V processor cores. It sup...

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.

The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct (SEU) errors in all on-chip RAM memories.

The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and suitable for system-on-chip (SOC) designs.