In cryptography, an attack can be performed by injecting one or several faults into a device, thus, disrupting its functional behavior. Commonly used techniques to inject faults consists of introducin...

The HSM IP module is a Hardware Security Module for automotive applications. It is developed, validated and licensed by Silex Insight (partner of Xilinx) as an FPGA-based IP solution dedicated to the ...

As part of Secure-IC s iSSP (integrated Security Service Platform), Secure-IC is able to provide integrated Secure Elements (iSE) that can act as trust anchors that protect the security assets of a de...

Secure Boot | Firmware update in the field | Secure key storage | Cryptography algorithms off-loading

On OSI layer 3 (network layer), IPsec is the transport security protocol of choice. The BA454 is a very scalable engine implementing the IPsec standard for high throughput applications.

NEW VIDEO CODEC THAT WILL SHAPE THE FUTURE OF AV OVER IP DISTRIBUTION OVER 1GbE!

The Professional Audio/Video market moves rapidly to IP. The majority of the codecs developed for the ProAV i...

The VC-2 LD (Low Delay) codec is a lightweight video compression IP core with ultra-low latency，for ASIC/FPGA ready for UHD and 4K transport

The VC-2 HQ (High Quality) codec is a lightweight video compression IP core with ultra-low latency.

The video IP cores using CFA (Bayer, Quad-Bayer) produces visually lossless video quality. The algorithm adds minimal latency to the system while it offers super-resolution.

These boards are fully integrated boards that enable the development of ultra-low latency audio/video over IP products. The transmit and receive boards are productionready and reduce the cost of the system.

The eSecure IP is a single subsystem for RISC-V based SoC to address key security challenges, playing the role of root-of-trust. The module is highly flexible and fits all applications of the heteroge...

The AES-GCM Ultra-low latency crypto engine is targeted for CXL link encryption with an implementation of the AES-GCM algorithm compliant with the NIST SP 800-38D standard. The unique architecture ena...

The ARIA crypto engine includes a generic implementation of the ARIA algorithm which is the block cipher standard of South Korea.

The BA452 is a secure connection engine that can be used to off-load the compute intensive Public Key operations.

Our solution is a secure public key infrastructure engine that can be used to offload compute-intensive public key operations such as signature generations and verifications.

Chacha20-Poly1305 high performance IP core for authenticated encryption.

The Cryptographic Coprocessor (or CryptoSoc Accelerator) is a hardware IP core platform that accelerates cryptographic operations in System-on-Chip (SoC) environment on FPGA (Intel SoC, Xilinx Zynq) and ASIC.

The Hash Crypto Engine is flexible and optimized hash IP core compliant with FIPS 180-3 (HASH functions), FIPS 198 (HMAC function) and OSCCA (SM3). With a flexible wrapper supporting a wide selection...

The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by the U.S National Institute of Standards and Technology (NIST) in 2001. Galois Counter Mod...

The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by the U.S National Institute of Standards and Technology (NIST) in 2001. It is included in ...

Memory protection against reverse engineering and tampering Protecting raw memory content from malevolent access Memory protection from the beginning it is written Available with zero latency or high...

Secure-IC has several IP products relative to Post-Quantum Cryptography - Securyzr integrated Secure Elements (iSE) supports a dual boot based on classical cryptography and on post-quantum cryptogra...

The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash. It is often used to protect the source code from decompiling or reverse engineering. This solution inclu...

To answer the needs of high-performance systems, a new generation of powerful processors is being designed and deployed. These multi-core SoCs contain dedicated hardware accelerators that offload chal...

The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of China. It is compliant with the GBT.32907-2016 specification and c...

The BA418 is crypto engine IP core for SHA-3 hashing functions compliant to NISTS s FIPS 180-4 and FIPS 202 standards.

The SM4 crypto engine includes a generic & scalable implementation of the SM4 algorithm which is the block cipher standard of China.

The SM4-GCM Multi-Booster crypto engine is a scalable implementation of the SM4-GCM algorithm compliant with the standard GBT.32907-2016