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50 "Verification Platform" Solutions

1
ARC Debug Option for all ARC Cores
SmaRT is a hardware module that can be integrated into any system-on-chip (SoC) within the DesignWare ARC configurable architecture.

2
ARC SmaRT, optional Real-Time Trace debug
Rapid Program Tracing Spots Hard-To-Find Bugs

3
Automotive Safety Verification for ISO 26262
Functional safety verification is one of the most critical issues for automobile development. Safety-critical automotive chips require compliance to ISO 26262 ASIL requirements, extending far beyond functional verification.

4
Cadence Verification Suite
Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.

5
DesignWare IP Prototyping Kits
The DesignWare IP Prototyping Kits provide the essential hardware and software elements needed to reduce IP prototyping and integration effort and to enable designers to start implementing IP in an So...

6
DesignWare STAR Memory System
The DesignWare® Self-Test and Repair (STAR) Memory System® is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or non-repairable embedded memories across any foundry or process node.

7
FineSim
FineSim is a high-performance accelerated SPICE simulator. FineSim s unique multi-core/multi-machine simulation capability allows users to drastically improve simulation performance and capacity.

8
FineSim Multi-Core/Multi-Machine Enabled Full-Chip Circuit-Level Simulation
FineSim? is a high-performance circuit simulator with built-in full SPICE and FastSPICE simulation engines. FineSim s unique multi-core/multi-machine simulation capability allows users to drastically ...

9
HAPS-80D Prototyping Solution
Desktop Prototyping Solution Enables Direct Design Interaction for Pre-Silicon Software Development and Testing

10
IP Prototyping Kit for DWC USB 3.1 Device Controller on HAPS-DX7, SuperSpeedPlus PHY, Type-C, PCIe connection for PC
IP Prototyping Kit for DWC USB 3.1 Device Controller on HAPS-DX7, SuperSpeedPlus PHY, Type-C, PCIe connection for PC

11
Palladium Z1 Enterprise Emulation System

Verification has become the biggest challenge in SoC development. However, traditional verification tools have not kept pace with how quickly SoC and ASIC design size and complexity are growing. Si...


12
Perspec System Verifier
Frustrated by all of the manual effort and time you're spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days.

13
Protium S1 FPGA-Based Prototyping Platform
The Protium™ S1 FPGA-Based Prototyping Platform is the latest generation prototyping solution enabling early software development, throughput regressions, and high-performance system validation. It combines high-capacity FPGA boards, based on Virtex-Ultrascale FPGAs, with a complete implementation and debug software suite, providing ultra-fast design bring-up and unprecedented ease of use.

14
ProtoCompiler
Prototypes for pre-silicon system validation and hardware/software integration are essential for today s IP and SoC design teams. But development schedules are short and the brief time from RTL drop ...

15
VIP for DisplayPort 2.0
The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K.

16
Xcelium Simulation on Arm-Based Servers
Verifying that system-on-chip (SoC) designs function correctly prior to manufacturing is a massive task requiring high-performance computing (HPC).

17
ZeBu-Blade2 Fast ASIC Desktop Emulator
The ZeBu-Blade2 hardware-assisted verification platform is the newest member of the ZeBu emulation family, and the first based on Xilinx Virtex6-LX760 field programmable gate arrays (FPGAs). Emulating...

18
Zebu-Server: One Billion Gate, Multi-User/Mode ASIC and SOC Emulation
ZeBu-Server is an extremely high capacity system emulator with the easy setup and debugging associated with emulation, and the price/performance of rapid prototyping. Supporting multiple users, interf...

19
ZSP-USB-JTAG Emulator
The ZSP-USB-JTAG emulator probe enables efficient and productive embedded software debugging. This compact and portable probe is powered by the USB port and utilizes the JTAG interface for debugging Z...

20
Embedded PVT monitoring IP solutions
Embedded Process, Voltage and Temperature (PVT) monitoring intellectual property (IP) for advanced node System on Chip (SoC) designs for performance optimisation and statistical analysis for enhanced design enablement.

21
In-Chip Monitoring Subsystem Solutions
The PVT Controller is a single interface to Moortec embedded Process, Voltage and Temperature (PVT) sensing fabric. By incorporating the PVT Controller, IC developers can benefit from our extended range of compelling features.

22
Moortec In-Chip Monitoring Subsystem on TSMC 16FFC
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices.

23
Moortec In-Chip Monitoring Subsystem on TSMC 7FF
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices. TSMC 7FF

24
PVT SubSystem
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices.

25
SD Express Card Verification IP
Truechip's SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of an ASIC/FPGA or SoC.

26
Display port 2.0 VIP
Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other data between a source device and sink device. Display port 2.0 VIP can be used to verify transmitter or Receiver device following the Display port basic protocol as defined in Display port 2.0.

27
NVM Express VIP (NVMe)
NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance.

28
OpenCAPI VIP
The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces.

29
TileLink VIP
TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC.

30
Analytics and optimization
By integrating fit-for-purpose non-intrusive monitoring and profiling blocks into the hardware design, the engineering team can obtain actionable intelligence from the real silicon, that they can use to tune performance parameters.

31
Deep capture / high visibility Debug IP for Intel FPGA
The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

32
Deep capture / high visibility Debug IP for Xilinx FPGA
The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

33
In-field
Use of on-chip processing allow the system manufacturer to enable development and optimization to be performed on the finished system, even after the device is shipped.

34
Inflexion UI
Mentor Embedded™Inflexion™ UI enables users to implement compelling and visually rich user interfaces (UIs) with significantly reduced effort; allowing users to meet the UI demands of toda...

35
Multi-domain simulation at the system-level for mixed signal behavior modeling
VisualSim Simulation Technology - heterogeneous models of computation

36
Performance modeling using stochastic components
In VisualSim Architect, one can model designs as stochastic processes, with library blocks and simulators supporting the same. The latency, in seconds, and throughput, measured in Mbps, gives the efficiency of the stochastic process. Designer can put into use, different use cases and get the expected output.

37
SILKAN ControlBuild
ControlBuildTM : A global software platform designed to develop and validate embedded control systems

38
SoC Debug
The average SoC now has more than 100 IP blocks. Such devices are powerful, but there is a problem: they are so complex that it is effectively impossible to understand how they operate in every circumstance.

39
Veloce Emulation Systems
The Veloce verification system reduces project schedules and cost through high-performance simulation acceleration and in-circuit emulation of complex SoC designs. Veloce achieves these benefits throu...

40
VisualSim Explorer
VisualSim Explorer is a Web Server that enables models to be embedded in documents for viewing, simulation and analysis from within a Web Browser without any local software installation. The technolog...

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