38 "Image" Solutions

CDNN Deep Learning Compiler
The CEVA Deep Neural Network (CDNN) is a comprehensive compiler technology that creates fully-optimized runtime software for CEVA-XM Vision DSPs and NeuPro AI processors. Targeted for mass-market embedded devices, CDNN incorporates a broad range of network optimizations, advanced quantization algorithms, data flow management and fully-optimized compute CNN and RNN libraries into a holistic solution that enables cloud-trained AI models to be deployed on edge devices for inference processing.

CEVA-SLAM SDK and Vision Software Libraries
The Application Developer Kit (ADK) for CEVA-XM and NeuPro streamlines the software development and integration effort required for advanced vision and AI applications. It enables entire applications to be run in a more familiar CPU environment, while automatically translating and optimizing code on the more power-efficient DSP.

CEVA-XM4 Imaging & Vision DSP
The CEVA-XM4 imaging and computer vision processor IP solves the most critical issues for the development of energy-efficient embedded vision systems where die size and power budget are extremely constrained, yet algorithms require intensive processing.

CEVA-XM6 Vision & Deep Learning DSP
The CEVA-XM6 is a fifth-generation imaging and computer vision processor IP from CEVA, and is designed to bring deep learning and artificial intelligence capabilities to low-power embedded systems, targeting mass-market intelligent vision applications.

Mali-G72 High Performance GPU
Arm® Mali™-G72 is the second generation Bifrost-based GPU for High Performance products.

5Mpixel ISP IP - 5M pixel sensor support Image Signal Processing (ISP) IP
Chips&Media s Camera ISP IP – LEDA is the Imaging Signal Processing (ISP) targeted to be used in low light environment

Lossless & Near-Lossless JPEG-LS Encoder
The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO/IEC 14495-1 standard.

Multi (2) Exposures HDR - Multi (2) Exposures High Dynamic Range (HDR) IP
NIX is multi-exposure high dynamic range IP, commonly known as HDR, which is based on 2 exposures blending (long and short exposures).

PowerVR G6630 GPU graphics processor
The PowerVR Series6 family delivers a significant portfolio of new technologies and features, including: an advanced scalable compute cluster architecture; high efficiency compression technology inclu...

PowerVR Series8XE GPU Family
The PowerVR Series8XE family of GPUs drives cost reduction in entry-level and mass market devices by offering 2 pixels/clock and 4 pixels/clock versions optimized to deliver the best user experience in a limited silicon area budget. This GPU family enables low-cost devices to benefit from the latest apps by supporting the most advanced APIs from Khronos, including OpenGL ES 3.2 and Vulkan 1.0.

PowerVR Series8XT Core
The PowerVR GT8525 is the first PowerVR 8XT core to be launched. It is based on the new Furian architecture, and brings about the advantages of that leading architecture

PowerVR Series9XE GPU Family
PowerVR Series9XE GPUs are a new generation of PowerVR GPUs based on the PowerVR Rogue architecture, that raise the bar on graphics and compute in cost-sensitive devices, letting SoC vendors achieve a...

PowerVR Series9XM GPU Family
PowerVR Series9XM GPUs are a new generation of PowerVR GPUs based on the PowerVR Rogue architecture, that raise the bar on graphics and compute in cost-sensitive devices, letting SoC vendors achieve a...

Window Motion Adaptive (MA) based 3DNR - Window MA based 3D Noise Reduction IP
HYDRA is temporal noise reduction IP, commonly known as 3DNR, which is based on Windows MA (motion adaptive) providing small IP size.

H.266/VVC Compliance Test Suite for Video Decoder Validation
Allegro DVT compliance bitstreams are designed for intensive testing of H.266/VVC 1 decoder implementations.

JPEG XS - the new low complexity codec standard for professional video production
JPEG XS stands for extra speed and extra small. The new ISO mezzanine codec standard co-developed by the Fraunhofer Institute for Integrated Circuits enables interoperability and allows an easy and cost effective integration into IP based infrastructure.

2D graphics- BADGE- BitSim Accelerated Display Graphics Engine
A configurable block with an advanced 2D graphics controller for both ASIC and FPGA that offloads your processor system.

Camera Multiple Receiver 2.5Gbps 8-Lane
The Camera Multiple (Combo) Receiver 2.5Gbps 8-Lane is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.

NEMA | dc
NEMA|dc is not just an ordinary display controller, it is a real Swiss Army Knife which contains several smart tools and functions to compose multiple graphics and video layers by improving image quality and help to reduce the SoC power consumption.

NEMA | t
The smallest Internet-of-Things (IoT) Graphics Processor Unit (GPU) with 3D functionality. The architecture of NEMA|t has been specifically designed from bottom-up for the new generation of superior wearable and IoT display products which require great graphics quality and performance and ultra-low power consumption.

intoPIX has made significant intellectual property development in lightweight low latency video compression, from inventing and standardizing the world's smallest and fastest mezzanine compression technology TICO (SMPTE RDD35) supported by the TICO Alliance, to being the proponent and co-developer of creating the world first international ISO standard technology JPEG XS , addressing this matter.

Ultra High Definition 4K & 8K JPEG 2000 Encoders & Decoders IP-cores
JPEG 2000 for extreme resolutions and UltraHDTV

IPB-PNG-E 24-bit 20-fps Portable Network Graphics Encoder
The IPB-PNG-E core can be used in systems on chip for encoding picture streams using the Portable Network Graphics (PNG) format. It has been designed for systems requiring high frame rate while encoding RGB images at 24-bit color depth.

LCD/TFT Controller ver. 2.00
The DCD BLCD32 core is a fully configurable, universal LCD/TFT display controller. It supports a wide range of resolution and enables both, horizontal and vertical synchronization parameters s...

M25 DSC 1.2 Decoder
The M25 DSC 1.2 Decoder offers real time decompression of HD streams with resolutions from 480p up to 8K. The decoder core is fully compliant with the VESA DSC 1.2 standard and is available for both FPGA and ASIC platforms.

Milbeaut Image Processor SC2000
“SC2000” is the latest SoC of the “Milbeaut® series”. Equipped with a digital signal processor optimized for computer vision, it also features advanced functionalities suc...

VESA DSC 1.1 Video Decoder IP Core
VESA DSC 1.1 compliant Video Decoder IP Core.

VESA DSC 1.1 Video Encoder IP Core
VESA DSC 1.1 compliant Video Encoder IP Core.

VESA DSC 1.2a Video Decoder IP Core
VESA DSC 1.2a compliant Video Decoder IP Core

VESA DSC 1.2a Video Encoder IP Core
VESA DSC 1.2a compliant Video Encoder IP Core

H.264 Encoder IP Core
The H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. It currently is the only H.264 encoder permitting UltraHD 4K 60 on low-range FPGAs and 8K 30 on mid-range Arria 10 and Zynq 7030 FPGAs.

HDMI-CEC - Consumer Electronics Control 1.4/2.0 IP
FPGA proven HDMI-CEC Controller IP that could be easily integrated into customer’s systems with minimum effort due to its highly area optimization and different operating clock modes.

HDR Image Signal Processor
Pinnacle Imaging Systems offers numerous, affordable Denali-MC HDR ISP licensing options for your camera development projects. Pinnacle?s Denali-MC can be utilized as a full, camera-ready, end-to-end HDR ISP, which contains 3 primary IP blocks, each providing individualized functionality.

HX6963 - Super High Resolution (SHR) IP
Super High Resolution (SHR) IP provides high quality images when low-resolution images are expanded and displayed in high-resolution. It can also be applied in camera application by model to eliminate blur, reduce noise and take sharper, clearer photos, providing high quality digital zoom in function for camera application.

HX6967 - SunLight Readable IP
SunLight Readable IP provides high-quality contrast optimization for a wide range of input image or video. SLR is a real-time image processing engine for automatic contrast adjustment under any ambient light environment.

Imaging and Video
Applications such as Drones, Machine Vision, Thermal Imaging, Gaming, Video Surveillance, Robotics, Advanced Driver Assistance Systems (ADAS) and HMI often use cameras and displays.

JPEG Encoder - baseline DCT compression
The JPEG Encoder IP core developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder.

mcCAP : Custom Application Platform
The new design approach to SoC reuse platform can be realized by using mcCAP solution based on MCSC technology.








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