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Monitoring and Verification
 Emulator and Prototyping (8)
 Monitoring and Debugging (13)
 Simulation and Verification (15)
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36 "Monitoring and Verification" Solutions

1
ZSP-USB-JTAG Emulator
The ZSP-USB-JTAG emulator probe enables efficient and productive embedded software debugging. This compact and portable probe is powered by the USB port and utilizes the JTAG interface for debugging Z...

2
Analog FastSPICE Platform

Foundry-certified, the AFS Platform delivers nm SPICE accuracy >5x faster than traditional SPICE and >2x faster than parallel SPICE simulators. Offering the world s fastest nm circuit verification ...

3
Analytics and optimization

System designers can use Tessent Embedded Analytics SoC monitoring and analytics features to refine performance based on the in-silicon behavior of their SoCs.

All too often, the real-world ...

4
In-field
Use of on-chip processing allow the system manufacturer to enable development and optimization to be performed on the finished system, even after the device is shipped.

5
Proteus
A one-stop software platform which applies analytics to data created by on-chip Agents™

6
SD Express Card Verification IP
Truechip's SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of an ASIC/FPGA or SoC.

7
SoC Debug
The average SoC now has more than 100 IP blocks. Such devices are powerful, but there is a problem: they are so complex that it is effectively impossible to understand how they operate in every circumstance.

8
Veloce Emulation Systems
The Veloce verification system reduces project schedules and cost through high-performance simulation acceleration and in-circuit emulation of complex SoC designs. Veloce achieves these benefits throu...

9
Corvette-F1 N25
Corvette-F1 N25 is an Amazon FreeRTOS-qualified, Arduino-compatible and FPGA-based evaluation platform.

10
Display port 2.0 VIP
Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other data between a source device and sink device. Display port 2.0 VIP can be used to verify transmitter or Receiver device following the Display port basic protocol as defined in Display port 2.0.

11
Fastest Power Emulator for Hardware-Software Power Verification
ZeBu® Empower delivers breakthrough performance for fast hardware-software power verification. Its performance enables multiple iterations per day with actionable power profiling in the context of...

12
High Throughput Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel and can support very high throughput rates up to 10 Gbps.

13
In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring
A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a complete subsystem dedicated to maximizing performance, optimizing power, reliability and enablin...

14
NVMe-Xactor VIP Solution
NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance.

15
OpenCAPI VIP
The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces.

16
PVT Controller (Series 4) (Sub-system for complete PVT monitoring)
The PVT Controller provides a standard digital interface to the embedded Process, Voltage and Temperature (PVT) sensing Sub-System used to increase System on Chip performance and reliability. On-chip ...

17
SHS is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores

The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores, including analog/ mixed-si...

18
SimAccel FPGA-Accelerated Verification
Accelerate RTL Verification and SW Bring-up Target IPs and SoCs
  • NVMe controller
  • PCIe RC/EP IP, Repeater, Switch
  • Flash controller
  • AMBA NoCs and peripherals
  • M...

19
SimCluster GLS
Gate-Level Parallel Simulation : Reduce Time to Simulation Sign-off

20
SimXACT - Gate Simulation Productivity and Analysis Technology
Gate-Level X-Verification : Reduce Bring-up Time

21
SMS is a comprehensive, integrated test, repair and diagnostics solution
The DesignWare® Self-Test and Repair (STAR) Memory System™ is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or nonrepairable embedded memories across any f...

22
TileLink VIP
TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC.

23
Deep capture / high visibility Debug IP for Intel FPGA
The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

24
Deep capture / high visibility Debug IP for Xilinx FPGA
The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

25
Enhanced Services Controller - Performance Monitoring
The MESC_PM3X function, implemented on a Spartan II FPGA, is to extend the functionnality already available within the APC. This macro can be customized according to specific needs (application-specif...

26
Multi-domain simulation at the system-level for mixed signal behavior modeling
VisualSim Simulation Technology - heterogeneous models of computation

27
Performance modeling using stochastic components
In VisualSim Architect, one can model designs as stochastic processes, with library blocks and simulators supporting the same. The latency, in seconds, and throughput, measured in Mbps, gives the efficiency of the stochastic process. Designer can put into use, different use cases and get the expected output.

28
VisualSim Explorer
VisualSim Explorer is a Web Server that enables models to be embedded in documents for viewing, simulation and analysis from within a Web Browser without any local software installation. The technolog...

29
Cadence Verification Suite
Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.

30
Palladium Z1 Enterprise Emulation System

Verification has become the biggest challenge in SoC development. However, traditional verification tools have not kept pace with how quickly SoC and ASIC design size and complexity are growing. Si...

31
Perspec System Verifier
Frustrated by all of the manual effort and time you're spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days.

32
Protium S1 FPGA-Based Prototyping Platform
The Protium™ S1 FPGA-Based Prototyping Platform is the latest generation prototyping solution enabling early software development, throughput regressions, and high-performance system validation. It combines high-capacity FPGA boards, based on Virtex-Ultrascale FPGAs, with a complete implementation and debug software suite, providing ultra-fast design bring-up and unprecedented ease of use.

33
VeriTiger-DH4000T FPGA Prototyping
VeriTiger Series FPGA prototyping board provides Rapid Prototyping Platform for various types of digital circuit design, greatly shortening the development cycle of SOC / IP and FPGA

34
VIP for DisplayPort 2.0
The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K.

35
Xcelium Simulation on Arm-Based Servers
Verifying that system-on-chip (SoC) designs function correctly prior to manufacturing is a massive task requiring high-performance computing (HPC).

36
POR, Power-on-Reset and Supply Monitoring

The S3PORT40LP is a low-power reset circuit that provides following features:

Power-on Reset (POR) signal that monitors absolute value of three power supplies. POR signal includes programmab...

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