Monitoring and Verification

www.design-reuse-china.com

从IP到片上系统以及物联网扫描上方二维码关注我们的微信号哦! IP SoC 中国2021！打开！立即加入！新闻视频加入D&R 社区

Emulator and Prototyping (7)

Monitoring and Debugging (13)

Simulation and Verification (18)

Fastest Power Emulator for Hardware-Software Power Verification

ZeBu® Empower delivers breakthrough performance for fast hardware-software power verification. Its performance enables multiple iterations per day with actionable power profiling in the context of...

In-Chip Monitoring Subsystem for Process, Voltage & Temperature (PVT) Monitoring

A full suite of embedded monitoring IP managed by a PVT controller with standard interfaces, creates a complete subsystem dedicated to maximizing performance, optimizing power, reliability and enablin...

PVT Controller (Series 4) (Sub-system for complete PVT monitoring)

The PVT Controller provides a standard digital interface to the embedded Process, Voltage and Temperature (PVT) sensing Sub-System used to increase System on Chip performance and reliability. On-chip ...

SHS is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores

The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores, including analog/ mixed-si...

SMS is a comprehensive, integrated test, repair and diagnostics solution

The DesignWare® Self-Test and Repair (STAR) Memory System™ is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or nonrepairable embedded memories across any f...

VC Functional Safety Manager

VC Functional Safety Manager provides a comprehensive tool for IP and semiconductor groups targeting functional safety certification for ISO 26262, IEC 61508 and other functional safety standards. It ...

ZSP-USB-JTAG Emulator

The ZSP-USB-JTAG emulator probe enables efficient and productive embedded software debugging. This compact and portable probe is powered by the USB port and utilizes the JTAG interface for debugging Z...

POR, Power-on-Reset and Supply Monitoring

The S3PORT40LP is a low-power reset circuit that provides following features:

Power-on Reset (POR) signal that monitors absolute value of three power supplies. POR signal includes programmab...

MimicPro FPGA PROTOTYPING SYSTEM

The Corigine©MimicProPrototyping System is a high-performance,FPGA-based system that raises prototyping to an unprecedented new level.

Proteus

A one-stop software platform which applies analytics to data created by on-chip Agents™

Analog FastSPICE Platform

Foundry-certified, the AFS Platform delivers nm SPICE accuracy >5x faster than traditional SPICE and >2x faster than parallel SPICE simulators. Offering the world s fastest nm circuit verification ...

Analytics and optimization

System designers can use Tessent Embedded Analytics SoC monitoring and analytics features to refine performance based on the in-silicon behavior of their SoCs.

All too often, the real-world ...

Display port 2.0 VIP

Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other data between a source device and sink device. Display port 2.0 VIP can be used to verify transmitter or Receiver device following the Display port basic protocol as defined in Display port 2.0.

In-field

Use of on-chip processing allow the system manufacturer to enable development and optimization to be performed on the finished system, even after the device is shipped.

NVMe-Xactor VIP Solution

NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance.

OpenCAPI VIP

The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces.

SD Express Card Verification IP

Truechip's SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of an ASIC/FPGA or SoC.

SimAccel FPGA-Accelerated Verification

Accelerate RTL Verification and SW Bring-up Target IPs and SoCs

NVMe controller
PCIe RC/EP IP, Repeater, Switch
Flash controller
AMBA NoCs and peripherals
M...

SimCluster GLS

Gate-Level Parallel Simulation : Reduce Time to Simulation Sign-off

SimXACT - Gate Simulation Productivity and Analysis Technology

Gate-Level X-Verification : Reduce Bring-up Time

SoC Debug

The average SoC now has more than 100 IP blocks. Such devices are powerful, but there is a problem: they are so complex that it is effectively impossible to understand how they operate in every circumstance.

TileLink VIP

TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC.

Veloce Emulation Systems

The Veloce verification system reduces project schedules and cost through high-performance simulation acceleration and in-circuit emulation of complex SoC designs. Veloce achieves these benefits throu...

Corvette-F1 N25

Corvette-F1 N25 is an Amazon FreeRTOS-qualified, Arduino-compatible and FPGA-based evaluation platform.

DEV - Virtual Platform Development and Simulation

The Imperas Developer products consist of tools, models and infrastructure components critical for the high quality, rapid development and verification of embedded software, utilizing virtual platform...

Enhanced Services Controller - Performance Monitoring

The MESC_PM3X function, implemented on a Spartan II FPGA, is to extend the functionnality already available within the APC. This macro can be customized according to specific needs (application-specif...

Fault Injection Studio

Fault Injection Attacks (FIA) extract secrets, e.g. cryptographic keys, from hardware systems by injecting faults, e.g. using a laser beam to disrupt the circuit function, or increasing operating freq...

High Throughput Additive White Gaussian Noise Generator

A configurable AWGN generator that can be used as emulator of a noisy transmission channel and can support very high throughput rates up to 10 Gbps.

ISS - The Imperas Instruction Set Simulator

Instruction Set Simulator (ISS) - fast, simple, easy to use, cross software development for embedded systems The Imperas ISS is often the first simulation product used in an embedded software develop...

M*SDK - Advanced Multicore Software Development Kit

The focus of the Imperas products is to save engineering time in the development of embedded software, primarily achieved by making the engineering process significantly more efficient through the use...

Multi-domain simulation at the system-level for mixed signal behavior modeling

VisualSim Simulation Technology - heterogeneous models of computation

Performance modeling using stochastic components

In VisualSim Architect, one can model designs as stochastic processes, with library blocks and simulators supporting the same. The latency, in seconds, and throughput, measured in Mbps, gives the efficiency of the stochastic process. Designer can put into use, different use cases and get the expected output.

QuantumLeap - Virtual Platform Simulation Acceleration

QuantumLeap is a parallel simulation performance accelerator that leverages a new synchronization algorithm to provide the fastest virtual platform software execution speed available. The execution pe...

Side Channel Studio

Side-Channel Attacks (SCA) extract cryptographic keys from hardware systems by analyzing power traces or electromagnetic emission data from the target device along with the corresponding collection of...

VisualSim Explorer

VisualSim Explorer is a Web Server that enables models to be embedded in documents for viewing, simulation and analysis from within a Web Browser without any local software installation. The technolog...

Deep capture / high visibility Debug IP for Intel FPGA

The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

Deep capture / high visibility Debug IP for Xilinx FPGA

The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

Prodigy Complete Prototyping Solutions

S2C's Prodigy Complete Prototyping Solutions addresses the need for a comprehensive solution that operates at any functional design stage, with any design size, and across multiple geographical lo...

Back

业务合作

广告发布

添加产品

© 2021 Design And Reuse