Interconnect, D2D, C2C SoC Catalog

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Interconnect, D2D, C2C Catalog

Chip to Chip (3)

Die-to-die (28)

Intra SoC Connectivity (9)

Network Interconnect (10)

1

16G UCIe Advanced PHY for TSMC 3nm

UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

2

16G UCIe Standard PHY for TSMC 3nm

UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

3

16G UCIe Standard PHY for TSMC 7nm

UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

4

2-16Gbps Die-to-Die (D2D) Multi-Protocol IO Supporting BOW, OHBI and UCIe

AresCORE is a market leading extremely low-power, low-latency interface IP designed by Alphawave IP for very high bandwidth connections between two dies that are on the same package.

5

25-112Gbps Extra Short-Reach (XSR) Multi-Standard SerDes (MSS)

The Alphawave DieCORE delivers the world s highest density, lowest power die-to-die connectivity solution for MCMs based on OIF XSR/USR serial standards. The DieCORE is a companion IP to the AlphaCOR...

6

40G Ultralink D2D PHY for GF12LP+

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

7

40G Ultralink D2D PHY for Samsung 7LPP

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

8

40G Ultralink D2D PHY for TSMC 3nm

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

9

40G Ultralink D2D PHY for TSMC 5nm

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

10

40G Ultralink D2D PHY for TSMC 7nm

Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

11

D2D PHY (Die-to-Die Interface)

Die-to-Die (D2D) PHY IP is based on HBM electrical specification and will also be compatible with upcoming interface standards. It is used specifically for heterogenous chiplet solutions in wired comm...

12

D2D Controller IP (Die-to-Die Interface)

OpenFive s Die-to-Die (D2D) Controller IP is targeted for heterogenous chiplet solutions in wired communications, AI and HPC applications. With recent advances in package technologies, it is possible ...

13

DesignWare Die-to-Die Controller IP with AXI Interface

The DesignWare Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, networking and high-performance comput...

14

DesignWare Die-to-Die Controller IP with AXI Interface

The DesignWare Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity in server, AI accelerator, networking and high-performance computing...

15

DesignWare Die-to-Die PHY IP in TSMC N7 Process

The DesignWare Die-to-Die PHY IP enables high-bandwidth ultra and extra short reach interfaces in multi-chip modules (MCMs) for hyperscale data center, AI, and networking applications. The low-latency...

16

Universal Chiplet Interconnect Express (UCIe 1.0) Controller

Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols

17

Mobiveil RapidIO Controller (GRIO)

Generic RapidIO (GRIO) controller is a highly flexible and configurable IP to provide RapidIO interface on one side and a generic interface on the system side.

18

1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)

eTopus designs ultra-high speed mixed-signal semiconductor IP solutions for high-performance computing and data center applications. Our 1-56/112Gbps ultra-high speed SerDes IP is adopted by global Ti...

19

1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency

Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP-based SerDes, the first startup demonstrated 56Gb...

20

CodaCache Last-Level Cache IP

It is a configurable, standalone, non-coherent cache IP that delivers unique business value through its advanced last-level cache (LLC) architecture, improving system performance, data locality, sc...

21

FlexNoC 5 Network-on-Chip SoC Interconnect IP

Arteris IP FlexNoC 5 network-on-chip (NoC) physically aware interconnect IP improves development time, performance, power consumption, and die size of system-on-chip (SoC) devices for mobile, automoti...

22

FlexNoC Resilience Package

The Arteris FlexNoC Resilience Package provides hardware-based data protection for increased SoC reliability and functional safety.

23

FlexWay Interconnect IP

FlexWay 5 from Arteris is an essential entry-level IP generator for cost-efficient, high-performance network-on-chip (NoC) designs. It revolutionizes SoC development with optimized interconnects, r...

24

Innovative Ultra-High-Speed Chiplet Solution

Innosilicon INNOLINK™ IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chips as if they were all on the same bus. Chiplets, d...

25

Multi-Die interLink (GLink 2.3) IP

GUC multi-die interLink (GLink) IP provides world’s best class solution for high-bandwidth, low-power, low-latency multi-channel interconnection in a package for applications such as High Performance ...

26

Ncore Cache Coherent Interconnect IP

Multicore SoC design challenges.

Key challenges in multicore system-on-chip (SoC) designs include efficient inter-core communication and synchronization, maintenance of cache coherence...

27

TSMC CLN6FF/7FF Die-to-Die Interface PHY

IGAD2DX01A is a high speed die-to-die interface PHY which transmits data through INFO RDL channels. IGAD2DX01A contains 32 Tx lanes and 32 Rx lanes per slice and supports 8 slices in one PHY. Each Tx/...

28

Analog I/O + ESD protection for Die-2-die interfaces

Analog I/OS and power line ESD solutions All voltage domains (0.75V to 5V) Additional voltage (e.g. 12V in 28nm proven)

29

Scatter-Gather DMA - AXI4-Stream to/from AXI4 Memory Map Transfers

The Digital Blocks DB-DMAC-MC-AXI4-MM-STREAM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces.

30

2GBps Low Power D2D Interface

Custom die-to-die high-speed interface in 28nm process technology. The I/O cells are defined as TX only, and RX only, and have two modes of operation, standard full rail to swing, or a custom low nois...

31

600MBps Low Power D2D Interface in 16nm

Custom die-to-die interface in 16nm process technology. The I/O cell is bi-directional and has two modes of operation: standard rail-to-rail swing or a custom low-noise pseudo-differential interface. ...

32

BlueLynx Executable Generator Technology

BlueLynx™ technology revolutionizes the game in silicon design and engineering. Using proprietary technology, Blue Cheetah eliminates inefficiencies inherent in traditional silicon design processes while maintaining complete integrity.

33

Bunch of Wires [BoW] PHY IP

Blue Cheetah's Bunch of Wires [BoW] PHY IP design incorporates the maximum benefit of the Open Compute Project's (OCP) inter-chiplet PHY specification, targeting best in class power, performa...

34

Coherent Network-on-Chip (NOC)

Scalable and area efficient interconnect solution optimized for memory coherent systems

35

Coherent Network-on-chip (NoC) IP

C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It...

36

Coherent Network-on-chip (NoC) IP

C-NoC is a layered, scalable, configurable, and physically aware configurable NoC. It supports mesh, grid and torus topologies with simultaneous existence of both coherent and non-coherent traffic. It...

37

CXL 3.0 Dual Mode Controller

CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL cards has same form factor as PCIE , and can be used ...

38

CXL Host Device Dual mode controllers

Primesoc s CXL IP supports dual mode of Host and device , integrated with PCIE Gen5 and well tested.

39

Die-to-Die (D2D) Interconnect

Lightweight die-to-die interconnect solution optimized for highest performance with the lowest power and area overhead

40

Interconnect Technology

EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC application space.

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