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43 "Verification Platform" Solutions

1
Cadence Verification Suite
Applying innovative solution flows, automation tools, and best-in-class verification engines is necessary to overcome the resulting verification gap.

2
Palladium Z1 Enterprise Emulation System

Verification has become the biggest challenge in SoC development. However, traditional verification tools have not kept pace with how quickly SoC and ASIC design size and complexity are growing. Si...


3
Perspec System Verifier
Frustrated by all of the manual effort and time you're spending developing complex system-level coverage-driven tests to verify your system on a chip (SoC)? Cadence® Perspec™ System Verifier automates this entire process, reducing complex use-case scenario development from weeks to just days.

4
Protium S1 FPGA-Based Prototyping Platform
The Protium™ S1 FPGA-Based Prototyping Platform is the latest generation prototyping solution enabling early software development, throughput regressions, and high-performance system validation. It combines high-capacity FPGA boards, based on Virtex-Ultrascale FPGAs, with a complete implementation and debug software suite, providing ultra-fast design bring-up and unprecedented ease of use.

5
SHS is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores

The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing system-on-chips (SoCs) or designs using multiple IP/cores, including analog/ mixed-si...


6
SMS is a comprehensive, integrated test, repair and diagnostics solution
The DesignWare® Self-Test and Repair (STAR) Memory System™ is a comprehensive, integrated test, repair and diagnostics solution that supports repairable or nonrepairable embedded memories across any f...

7
VIP for DisplayPort 2.0
The Cadence® Verification IP (VIP) for DisplayPort 2.0 provides a complete bus functional model (BFM) with integrated automatic protocol checks. Incorporating the latest protocol updates, the DisplayPort 2.0 (10Gbps per lane) VIP builds on top of the mature and comprehensive VIP for DisplayPort 8K.

8
Xcelium Simulation on Arm-Based Servers
Verifying that system-on-chip (SoC) designs function correctly prior to manufacturing is a massive task requiring high-performance computing (HPC).

9
ZSP-USB-JTAG Emulator
The ZSP-USB-JTAG emulator probe enables efficient and productive embedded software debugging. This compact and portable probe is powered by the USB port and utilizes the JTAG interface for debugging Z...

10
Embedded PVT monitoring IP solutions
Embedded Process, Voltage and Temperature (PVT) monitoring intellectual property (IP) for advanced node System on Chip (SoC) designs for performance optimisation and statistical analysis for enhanced design enablement.

11
In-Chip Monitoring Subsystem Solutions
The PVT Controller is a single interface to Moortec embedded Process, Voltage and Temperature (PVT) sensing fabric. By incorporating the PVT Controller, IC developers can benefit from our extended range of compelling features.

12
Moortec In-Chip Monitoring Subsystem on TSMC 16FFC
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices.

13
Moortec In-Chip Monitoring Subsystem on TSMC 7FF
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices. TSMC 7FF

14
Moortec In-Chip Monitoring Subsystem on TSMC N5P
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices. TSMC N5P

15
PVT SubSystem
Within the Moortec embedded in-chip monitoring subsystem fabric the Process Monitor provides the means for advanced node Integrated Circuit (IC) developers to detect the process variation of core digital MOS devices.

16
SD Express Card Verification IP
Truechip's SD Express Card Verification IP provides an effective & efficient way to verify the components interfacing with SD Express Interface of an ASIC/FPGA or SoC.

17
Corvette-F1 N25
Corvette-F1 N25 is an Amazon FreeRTOS-qualified, Arduino-compatible and FPGA-based evaluation platform.

18
Display port 2.0 VIP
Display port 2.0 is the serial communication protocol developed by Video Electronics Standards Association(VESA) to support the video,audio and other data between a source device and sink device. Display port 2.0 VIP can be used to verify transmitter or Receiver device following the Display port basic protocol as defined in Display port 2.0.

19
NVMe-Xactor VIP Solution
NVMe-Xactor is a comprehensive VIP solution portfolio for NVMe 1.2 used by SoC and IP designers to ensure comprehensive verification and protocol and timing compliance.

20
OpenCAPI VIP
The SmartDV s OpenCAPI Verification IP is fully compliant with OpenCAPI Specification V3.0 and V3.1 and verifies OpenCAPI interfaces.

21
SimAccel FPGA-Accelerated Verification
Accelerate RTL Verification and SW Bring-up Target IPs and SoCs
  • NVMe controller
  • PCIe RC/EP IP, Repeater, Switch
  • Flash controller
  • AMBA NoCs and peripherals
  • M...

22
SimCluster GLS
Gate-Level Parallel Simulation : Reduce Time to Simulation Sign-off

23
SimXACT - Gate Simulation Productivity and Analysis Technology
Gate-Level X-Verification : Reduce Bring-up Time

24
TileLink VIP
TileLink Verification IP provides an smart way to verify the TileLink component of a SOC or a ASIC.

25
Analytics and optimization
By integrating fit-for-purpose non-intrusive monitoring and profiling blocks into the hardware design, the engineering team can obtain actionable intelligence from the real silicon, that they can use to tune performance parameters.

26
Deep capture / high visibility Debug IP for Intel FPGA
The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

27
Deep capture / high visibility Debug IP for Xilinx FPGA
The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of an FPGA design without having to store the full trace data in the FPGA.

28
In-field
Use of on-chip processing allow the system manufacturer to enable development and optimization to be performed on the finished system, even after the device is shipped.

29
Inflexion UI
Mentor Embedded™Inflexion™ UI enables users to implement compelling and visually rich user interfaces (UIs) with significantly reduced effort; allowing users to meet the UI demands of toda...

30
Multi-domain simulation at the system-level for mixed signal behavior modeling
VisualSim Simulation Technology - heterogeneous models of computation

31
Performance modeling using stochastic components
In VisualSim Architect, one can model designs as stochastic processes, with library blocks and simulators supporting the same. The latency, in seconds, and throughput, measured in Mbps, gives the efficiency of the stochastic process. Designer can put into use, different use cases and get the expected output.

32
SoC Debug
The average SoC now has more than 100 IP blocks. Such devices are powerful, but there is a problem: they are so complex that it is effectively impossible to understand how they operate in every circumstance.

33
Veloce Emulation Systems
The Veloce verification system reduces project schedules and cost through high-performance simulation acceleration and in-circuit emulation of complex SoC designs. Veloce achieves these benefits throu...

34
VisualSim Explorer
VisualSim Explorer is a Web Server that enables models to be embedded in documents for viewing, simulation and analysis from within a Web Browser without any local software installation. The technolog...

35
Display Emulation/Testing Platform
SiWave develops innovative solutions for the embedded market. We have been in business since 2003 and have successfully delivered a number of projects targeting different industry standards. We sell o...

36
FPGA Prototyping for Super-Definition Video Verification
VeriTiger-M2000T platform aims to meet the booming requirement for the prototyping verification to the Super-Definition and High-Definition Video SOC/IP development. As a new member of HyperSilicon Al...

37
High Level Synthesizable Models for MIPI M-PHY 3.0
M-PHY is a high-speed serial physical interface technology with flexible signal characteristics and high bandwidth capabilities, which is particularly developed for mobile applications that offer incr...

38
LPDDR4 DRAM Bus Monitor
This is implemented as per JDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system.

39
LPDDR4 DRAM Memory Model
This model is implemented as per JEDEC standard JESD209-4A and provides an effective & efficient way to verify the LPDDR4 components of an ASIC/FPGA system.

40
reVISION : Responsive and Reconfigurable Vision Systems
Leading system developers are using All Programmable Devices in next generation vision guided machine learning systems. To accelerate productivity, Xilinx has created the reVISION Zone to aggregate us...

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