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1132 Solutions

1
10G PHY for PCIe 2.0 in TSMC (7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


2
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


3
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


4
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


5
10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


6
10G TCP & UDP Offload Engines, Ultra Low latency
INT 25012 is the only SOC IP Core that implements a full 10G bit TCP and UDP Stack inHand crafted, Ultra-High Performance, Innovative, Flexible and Scalable architecture which can also be easily custo...

7
10G TCP+UDP Offload Engine+PCIe Ultra-Low Latency
INT 25012 is the only SOC IP Core that implements a full 10G bit TCP and UDP Stack in Handcrafted, Ultra-High Performance, Innovative, Flexible and Scalable architecture which can also be easily custo...

8
12G PHY

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


9
12G PHY in TSMC (28nm, 16nm, 12nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


10
12G PHY in UMC (28nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


11
16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


12
16G PHY in TSMC (28nm, 16nm, 12nm)

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


13
16nm FinFET+ Speedcore eFPGA
Speedcore embedded FPGA (eFPGA) IP for integration SoCs is designed for compute and network acceleration applications and is based on the same high-performance architecture that is in Achronix s Speedster 22i FPGAs.

14
25G PHY

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


15
25G PHY in TSMC (16nm, 12nm, 7nm)

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


16
32G PHY in TSMC (7nm)

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


17
40G TCP/UDP Offload Engine
INT 40011 is the only SOC IP Core that implements a full 40G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance, Innovative, Flexible and Scalable architecture which can also be easi...

18
50G//25G TCP/UDP Offload Engine
INT 25011 is the only SOC IP Core that implements a full 25G bit TCP Stack in Handcrafted, Ultra-Low latency and High Performance, Innovative, Flexible and Scalable architecture which can also be easi...

19
56G Ethernet PHY in TSMC (16nm, 7nm)

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measureme...


20
6G PHY in TSMC (16nm)

The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys' highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) c...


21
ACE software
ACE works in conjunction with industry-standard synthesis tools, allowing FPGA designers to easily map their designs into Achronix Speedster®22i FPGAs.

22
ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

23
ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

24
ARC AS200 Audio Family - Efficient Single/Dual Core Audio Processors, Optimized Codecs

Synopsys offers an extensive portfolio of audio codecs that are available for use with the DesignWare® ARC® EMxD and the ARC HS4x families of processors. The ARC audio codecs facilitate a range of...


25
ARC Debug Option for all ARC Cores
SmaRT is a hardware module that can be integrated into any system-on-chip (SoC) within the DesignWare ARC configurable architecture.

26
ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications

DesignWare EV Embedded Vision Processors provide high-performance processing capabilities at a power and cost point low enough for embedded applications, while maintaining flexibility to support an...


27
ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications

DesignWare EV Embedded Vision Processors provide high-performance processing capabilities at a power and cost point low enough for embedded applications, while maintaining flexibility to support an...


28
ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications

DesignWare EV Embedded Vision Processors provide high-performance processing capabilities at a power and cost point low enough for embedded applications, while maintaining flexibility to support an...


29
ARC SmaRT, optional Real-Time Trace debug
Rapid Program Tracing Spots Hard-To-Find Bugs

30
ARIA Crypto Engine
The ARIA crypto engine includes a generic implementation of the ARIA algorithm which is the block cipher standard of South Korea.

31
Arm Artisan IoT POP IP
Arm IoT POP IP helps accelerate the implementation of IoT SoCs by offering physical IP as well as reference designs and know-how to develop a design that has optimal performance with minimum area.

32
Arm 11MPCore Processor
The Arm 11MPCore Processor implements the Arm 11 microarchitecture and brings multicore scalability with 1 to 4 cores from a single RTL base, enabling simple system design with a single macro to integrate with up to 4x the performance of a single core

33
Arm Allinea Studio
High Performance Tools for Developing Arm Based HPC Solutions

34
Arm Cordio-B50
The Arm Cordio-B50 is a Bluetooth 5 modem, protocol processing logic and link layer controller delivered as soft IP, with power intent and implementation IP, associated testbenches and link layer firmware. Cordio-B50 supports changes enabled by the Bluetooth 5 radio including the 2 Mbps mode, Long range, and advertising extensions.

35
Arm Cordio-B50 radio IP
The Arm Cordio-B50 radio IP is a complete self-contained radio subsystem supporting Bluetooth 5 protocol available at TSMC 55nm LP/ULP, TSMC 40nm LP/ULP and UMC 55nm ULP process nodes. The solution consists of the RF 2.4GHz transceiver, modem, protocol processing logic and link controller along with link layer firmware.

36
Arm Cordio-B50 stack
The Arm Cordio stack is designed specifically for Bluetooth low energy single-mode products catering to the power sensitive Internet of Things (IoT) market. With its small code size, easy-to-use APIs, and portable architecture, the Cordio stack is a superior solution for companies looking to develop Bluetooth low energy semiconductors while reducing time-to-market.

37
Arm Cordio-C50
The Arm Cordio-C50 is a Bluetooth 5 modem, a 802.15.4-2006 modem, protocol processing logic and link and MAC layer controller delivered as soft IP, with powerintent and implementation IP, associated test-benches and link layer and MAC firmware.

38
Arm Cordio-C50 radio IP
Arm Cordio-C50 radio IP is a complete self-contained radio sub-system supporting Bluetooth 5 and IEEE 802.15.4 protocols available at TSMC 55nm LP/ULP, TSMC 40nm LP/ULP, and UMC 55nm ULP process nodes. The solution consists of the RF 2.4GHz transceiver, modem, protocol processing logic and link and MAC controller along with link and MAC layer firmware.

39
Arm Cordio-E154
The Arm Cordio-E154 is an 802.15.4-2006 modem, protocol processing logic and MAC layer controller delivered as soft IP, with power intent and implementation IP, associated test-benches and MAC firmware.

40
Arm Cordio-E154 radio IP
The Arm Cordio-E154 radio IP is a complete self-contained radio subsystem supporting the IEEE 802.15.4 protocol available at TSMC 55nm LP/ULP, TSMC 40nm LP/ULP and UMC 55nm ULP process nodes. The solution consists of the RF 2.4GHz transceiver, modem, protocol processing logic and MAC controller along with MAC layer firmware.

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