Design and Reuse Embedded - From Silicon on Chip Solutions to Asic Design Platforms

The ZeusCORE Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS) IP is the highest performance SerDes in the Alphawave product portfolio. It is a highly configurable IP that supports all leading edge NR...

10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto

The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3- 2008 standard. The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a...

100G AES Encryption Core

The 100G AES Encryption Core is a high performance and yet low footprint AES engine for 100G/s application. Typical applications are providing bulk encryption for 100GE, LO ODUCn and OTU4.

10G PHY for PCIe 2.0 in TSMC (7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...

10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...

10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...

10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...

128-bit vector word length ARC VPX2 DSP IP

DesignWare® ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on devices to automotive ADAS to communications and high-performa...

12G PHY

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...

12G PHY in TSMC (28nm, 16nm, 12nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...

12G PHY in UMC (28nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...

16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...

16G PHY in TSMC (28nm, 16nm, 12nm)

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...

2-16Gbps Die-to-Die (D2D) Multi-Protocol IO Supporting BOW, OHBI and UCIe

AresCORE is a market leading extremely low-power, low-latency interface IP designed by Alphawave IP for very high bandwidth connections between two dies that are on the same package.

24 Ghz / 77 Ghz Automotive Radar Transceivers IP

Driver assistance systems use radar sensors in various counts and configurations. The data provided by the radar sensors is used in applications such as blind-spot detection, autonomous emergency brak...

25-112Gbps Extra Short-Reach (XSR) Multi-Standard SerDes (MSS)

The Alphawave DieCORE delivers the world s highest density, lowest power die-to-die connectivity solution for MCMs based on OIF XSR/USR serial standards. The DieCORE is a companion IP to the AlphaCOR...

256-bit vector word length ARC VPX3 DSP IP

The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS applica...

256-bit vector word length, dual-core ARC VPX3 DSP IP with integrated hardware safety features for automotive

25G PHY

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...

25G PHY in TSMC (16nm, 12nm, 7nm)

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...

32G PHY in TSMC (7nm)

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...

3DES Crypto Engine

The DES/3DES crypto engine offers a hardware implementation of the Data Encryption Standard (DES) according to Federal Information Processing Standards Publication (FIPS 46-3) of the National Insti...

3DES-ECB 1 Billion trace DPA resistant cryptographic accelerator core

Rambus Crypto Accelerator 3DES-ECB Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumpti...

512-bit dual-core vector DSP IP

56G Ethernet PHY in TSMC (16nm, 7nm)

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measureme...

5G New Radio Release-15 BaseBand PHY. (L1) IP

This is a 3GPP 5G NR Release 15 Compliant g-NodeB solution. The solution adapts a modular Design with the clear interface between the various modules supporting various RAN functional splits.

5G New Radio Release-15 BaseBand Protocol Stack (L2-L3) Software IP

This is a 3GPP 5G NR Release 15 Compliant g-NodeB solution. The solution adapts a modular Design with the clear interface between the various modules supporting various RAN functional splits.

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5G New Radio Release-15 UE Protocol Stack (L1-L2) Software IP

This is a 3GPP 5G NR Release 15 Compliant UE Protocol Stack SW IP. The stack also offers LTE Stack functionality. It can operate in both SA and NSA mode. The single solution can support LTE, 5GNR a...

5G Ultra low power Sub-6 GHz RF Transceiver IP

This is a 3GPP compliant 5G Sub-6GHz RF Transceiver IP optimized for cellular application. It integrates all the necessary RF/analog/mixed signal functions for a 3GPP Universal/5G/4G/3G 2x2 transce...

5G Universal low power RF Transceiver IP optimized for cellular applications

This is a 3GPP compliant low power 3GPP 5G/4G/3G transceiver IP optimized for cellular applications. It integrates all the necessary RF/analog/mixed signal functions for a 3GPP

Universal/5G/4...

5G-4G Ultra low power Sub-4 GHz RF Transceiver IP

This is a 3GPP compliant low-power sub-4GHz 5G/ 4G RF Transceiver IP optimized for 5G / 4G applications. The silicon proven RF IP in TSMC 65nm, integrates all the necessary RF/analog/mixed-signal f...

6G PHY in TSMC (16nm)

The multi-lane DesignWare Multi-Protocol 6G PHY IP is part of Synopsys' highperformance multi-rate transceiver portfolio, meeting the growing needs for small area, low bill of materials (BOM) c...

ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process

Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete GDSII that includes analog BIST and routing to your pads.

ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade

Active mesh against tampering attacks - Active Shield

Attacks against digital circuits can be performed by directly tampering with the device s internal structure. These attacks are intrusive, and regroup attempts to directly probe or force signals, remo...

AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores

Rambus Crypto Accelerator AES-AE-Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consum...

AES (ECB-CBC-CFB-CTR), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores

Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the powe...

AES CCM/GCM Engine

The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O reg...

AES Engine

The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publication 197. The accelerators include I/O register...

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