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1785 SoCs

1
1-112Gbps Long-Reach (LR) Multi-Standard-Serdes (MSS)
The AlphaCORE Long-Reach (LR) Multi-Standard-Serdes (MSS) IP is a high-performance, low-power, DSP-based PHY

2
1-112Gbps Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS)
The ZeusCORE Xtra-Long-Reach (XLR) Multi-Standard-Serdes (MSS) IP is the highest performance SerDes in the Alphawave product portfolio. It is a highly configurable IP that supports all leading edge NR...

3
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3- 2008 standard. The Gigabit Ethernet IP provides a 10/100 Mbps Media Independent Interface (MII) and a...

4
10G PHY for PCIe 2.0 in TSMC (7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


5
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


6
10G PHY for PCIe 3.0 in TSMC (16nm) for Automotive

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


7
10G PHY for PCIe 3.0 in TSMC (16nm, 12nm, 10nm, 7nm)

The multi-lane DesignWare Multi-Protocol 10G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for low-power consumption and low latency i...


8
10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
Configurable MAC solutions for speeds from 10Gbps to 10Mbps

9
128-bit vector word length ARC VPX2 DSP IP
DesignWare® ARC® VPX DSP IP is a family of VLIW/SIMD processors targeting a broad range of signal processing applications, from always-on devices to automotive ADAS to communications and high-performa...

10
12G PHY

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


11
12G PHY in TSMC (28nm, 16nm, 12nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


12
12G PHY in UMC (28nm)

The multi-channel, multi-protocol DesignWare® Enterprise 12G PHY IP is part of Synopsys' high performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth in e...


13
16G PHY

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


14
16G PHY in TSMC (28nm, 16nm, 12nm)

The multi-lane DesignWare® Multi-Protocol 16G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio, meeting the growing needs for high bandwidth and low latency in ...


15
16G UCIe Advanced PHY for TSMC 3nm
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

16
16G UCIe Standard PHY for TSMC 3nm
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

17
16G UCIe Standard PHY for TSMC 7nm
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance bandwidth for die-to-die link interconnectivity

18
1G to 200G High Speed Channelized Ethernet Controller MAC/PCS/FEC
200G aggregate bandwidth channelized solution for up to four Ethernet channels

19
2-16Gbps Die-to-Die (D2D) Multi-Protocol IO Supporting BOW, OHBI and UCIe
AresCORE is a market leading extremely low-power, low-latency interface IP designed by Alphawave IP for very high bandwidth connections between two dies that are on the same package.

20
200G/400G High Speed Ethernet Controller MAC/PCS/FEC
200G/400G bandwidth solution for one Ethernet channel

21
24 Ghz / 77 Ghz Automotive Radar Transceivers IP
Driver assistance systems use radar sensors in various counts and configurations. The data provided by the radar sensors is used in applications such as blind-spot detection, autonomous emergency brak...

22
25-112Gbps Extra Short-Reach (XSR) Multi-Standard SerDes (MSS)
The Alphawave DieCORE delivers the world s highest density, lowest power die-to-die connectivity solution for MCMs based on OIF XSR/USR serial standards. The DieCORE is a companion IP to the AlphaCOR...

23
256-bit vector word length ARC VPX3 DSP IP
The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS applica...

24
256-bit vector word length, dual-core ARC VPX3 DSP IP with integrated hardware safety features for automotive
The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS applica...

25
25G PHY

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


26
25G PHY in TSMC (16nm, 12nm, 7nm)

The multi-lane DesignWare Multi-Protocol 25G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY is s...


27
32G PHY in TSMC (7nm)

The multi-lane DesignWare® Multi-Protocol 32G PHY IP is part of Synopsys' high-performance multi-rate transceiver portfolio for high-end networking and cloud computing applications. The PHY...


28
3DES-ECB 1 Billion trace DPA resistant cryptographic accelerator core
Rambus Crypto Accelerator 3DES-ECB Hardware Cores offload compute intensive cryptographic algorithms in SoC s CPU at 100x performance (when run at identical frequencies) and 10% of the power consumpti...

29
400G/800G High Speed Ethernet Controller MAC/PCS/FEC
800G/400G bandwidth solution for one Ethernet channel

30
400G/800G High Speed Ethernet Controller PCS/FEC
Up to 800G bandwidth solution for one Ethernet channel

31
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

32
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

33
40G Ultralink D2D PHY for TSMC 3nm
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

34
40G Ultralink D2D PHY for TSMC 5nm
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

35
40G Ultralink D2D PHY for TSMC 7nm
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity

36
512-bit dual-core vector DSP IP

The DesignWare ARC VPX5 DSP processor IP is a member of the VPX VLIW/ SIMD DSP family for high-end computation applications. The VPX5 processor is designed for high-performance automotive ADAS appl...


37
56G Ethernet PHY in TSMC (16nm, 7nm)

The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measureme...


38
5G New Radio Release-15 BaseBand PHY. (L1) IP

This is a 3GPP 5G NR Release 15 Compliant g-NodeB solution. The solution adapts a modular Design with the clear interface between the various modules supporting various RAN functional splits.


39
5G New Radio Release-15 BaseBand Protocol Stack (L2-L3) Software IP

This is a 3GPP 5G NR Release 15 Compliant g-NodeB solution. The solution adapts a modular Design with the clear interface between the various modules supporting various RAN functional splits.

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40
5G New Radio Release-15 UE Protocol Stack (L1-L2) Software IP

This is a 3GPP 5G NR Release 15 Compliant UE Protocol Stack SW IP. The stack also offers LTE Stack functionality. It can operate in both SA and NSA mode. The single solution can support LTE, 5GNR a...


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